Without limiting the scope of the invention, its background is described in connection with dynamic random access memory (DRAM) cells, as an example.
As is well known in the art of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area is defined by the geometries and sizes of the active components disposed in the wafer substrate. Active components include gate electrodes in metal-oxide semiconductors (MOS) and diffused regions such as MOS source and drain regions and bipolar emitters, collectors and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular equipment used for processing the integrated circuit.
A significant problem of current photolithographic techniques as applied to very-large-scale integration (VLSI) as more and more layers are added, is that additional steps add additional complexity to the creation of circuits on the wafer surface. The resolution of small image sizes in photolithography becomes more difficult due to light reflection and the thinning of the photoresist during processing.
As a two dimensional process used to achieve a three dimensional structure, the goal of photolithographic patterning is to establish the horizontal and vertical dimensions of the various devices and circuits used to create a pattern that meets design requirements, such as, the correct alignment of circuit patterns on the wafer surface. As line widths shrink, photolithography of patterns down to the nanometer level and smaller approach the limits of resolution of present equipment. These nanometer width lines become increasingly more difficult to pattern because of the need to isolate the integrated circuit components.
A DRAM cell consists of a transistor and a capacitor. A bitline and a wordline are connected to one of the transistor source/drain and its gate, with the other source/drain being connected to the capacitor. As the density of DRAM cells on a silicon chip increases, DRAM cells having three dimensional structures, such as stacked capacitors, have been developed to meet the increased need for miniaturization. The use of stacked three dimensional structures, for example, allows the DRAM designer to maximize the capacitance of storage nodes within the limited area of the DRAM cell.